BIST for embedded static RAMs with coverage calculation

Author

Van Sas, Jos ; Wauwe, Geert Van ; Huyskens, Erik ; Rabaey, Dirk

Author_Institution

Alcatel Bell Telephone, Antwerpen, Belgium

fYear

1993

fDate

17-21 Oct 1993

Firstpage

339

Lastpage

348

Abstract

The implementation of deterministic RAM self-test algorithms turns out to be very area-consuming when a single ASIC contains many small, deeply embedded RAMs. Therefore, we have opted to reuse and modify the existing functional logic and to use a combined deterministic pseudo-random self-test strategy. A novel fault coverage calculation method for this self-test strategy has been developed. The method is easy to use because it is fully integrated in a hardware description language based design environment. Results for a chip set for broadband ISDN show that the combination of pseudo-random data generation and deterministic addressing of the RAMs provides high fault coverage results. Circuitry overhead varies between 2 and 14% of the RAM surface

Keywords

ISDN; SRAM chips; application specific integrated circuits; automatic testing; built-in self test; fault diagnosis; hardware description languages; integrated circuit testing; BIST; SRAM; broadband ISDN; coverage calculation; deterministic RAM; deterministic addressing; embedded static RAMs; fault coverage; hardware description language; pseudo-random data generation; pseudo-random self-test strategy; self-test algorithms; single ASIC; Application specific integrated circuits; B-ISDN; Built-in self-test; Change detection algorithms; Circuit faults; Circuit testing; Logic devices; Logic testing; Random access memory; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1993. Proceedings., International

Conference_Location

Baltimore, MD

Print_ISBN

0-7803-1430-1

Type

conf

DOI

10.1109/TEST.1993.470679

Filename

470679