• DocumentCode
    1827420
  • Title

    The cost of quality: Reducing ASIC defects with IDDQ, at-speed testing, and increased fault coverage

  • Author

    Gayle, Rick

  • Author_Institution
    NCR Workstation Products Div., Liberty, SC, USA
  • fYear
    1993
  • fDate
    17-21 Oct 1993
  • Firstpage
    285
  • Lastpage
    292
  • Abstract
    This paper attempts to quantify the economic benefits of including improved design for test (DFT) strategies into the ASIC design process. The qualitative results of higher stuck-at fault coverage, IDDQ testing, and BIST, have been documented; the quantitative results and their economic impact have not. This paper presents real life costs associated with poor quality in order to justify the resource investments needed to support improved DFT strategies
  • Keywords
    application specific integrated circuits; built-in self test; design for testability; economics; electric current measurement; fault location; integrated circuit manufacture; ASIC defects; ASIC design; BIST; DFT; IDDQ; at-speed testing; design for test; economic benefits; fault coverage; life costs; quality; quantitative results; stuck-at fault coverage; Application specific integrated circuits; Circuit faults; Costs; Design for testability; Economic forecasting; Manufacturing; Production; Semiconductor device modeling; Testing; Workstations;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1993. Proceedings., International
  • Conference_Location
    Baltimore, MD
  • Print_ISBN
    0-7803-1430-1
  • Type

    conf

  • DOI
    10.1109/TEST.1993.470685
  • Filename
    470685
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1827420