Title :
Scan DFT: Why more can cost less
Author_Institution :
CrossCheck Technol. Inc., San Jose, CA, USA
Abstract :
Reducing "time to market" is one of the keys to success in an increasingly competitive business environment. Even a small delay in getting a product to market can have a significant negative impact on its profitability. A large proportion of the total design time for complex ASICs can be spent on test development. Therefore, test automation is becoming essential
Keywords :
application specific integrated circuits; automatic testing; design for testability; economics; integrated circuit manufacture; integrated circuit testing; logic testing; DFT; competitive business environment; complex ASICs; cost; delay; design time; profitability; scan design for testability; test automation; time to market; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Clocks; Costs; Design for testability; Logic arrays; Silicon; Time to market;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470692
