Title :
Ultra low cost advanced package solution -Cu via microstar CSP (CV-u*CSP) development
Author :
Ho, Jk ; Chen, Michael ; Li, Anderson
Author_Institution :
Texas Instrum. Taiwan Ltd., Taipei, Taiwan
Abstract :
This paper presents Texas Instruments (TI) MicrostarCSP™ (u*CSP™), and Cu Via MicrostarCSP (CV-u* CSP) packages developed in TI Taiwan. u*CSP™ is a new IC assembled packaging developed as a wire-bondable package with lower cost than a Wafer Chip Scale Package (WCSP). The u*CSP™ package was successfully developed in year 2008, and has been mass- produced since year 2009 for Video Driver application. u*CSP™ results in 70% cost reduction due to significant shrinkage in die size for same IO count in comparison with a WCSP for same package footprint and thickness. u*CSP™ package requires 60% die size of WCSP, and saves 25% package foot print size by using the photo sensitive type solder resist instead of thermo-setting. It was also successful in applying Reversed Standoff Stitch Bond (RSSB) to achieve short wire length with ultra low loop in order to satisfy thin package needs. CV-u*CSP package mainly differs from u*CSP™ in terms of solder ball and substrate. It is developed as a high- throughput and low cost package by addressing both materials and processes used in the assembly flow in order to achieve lowest package cost. CV-u*CSP is assembled with the protruded copper via substrate instead of existing via hole type substrate which needs to be attached with additional solder bumps. The removal of a large portion of Au plating thickness and Solder Resist (S/R) are other differences between CV-u*CSP and u*CSP™ Quality and reliability of CV-u*CSP has been validated via extensive evaluation plans recently, and the benefits of the solution among low cost wire bond package families is confirmed. The results are expected to significantly reduce the cost of the package due to the following important features. 1) Removal of ball attach process from substrate package 2) Removal of solder resists 3) Competes with WCSP in package size and thickness.
Keywords :
integrated circuit metallisation; integrated circuit reliability; lead bonding; wafer level packaging; Au; CV-u*CSP; Cu; IC assembled packaging; Texas Instruments MicrostarCSP; copper via microstar CSP development; package Quality; package reliability; photo sensitive type solder resist; plating thickness; reversed standoff stitch bond; solder resist; solder resists removal; substrate package; ultra low cost advanced package solution; wafer chip scale package; wire bondable package; Copper; Gold; Reliability; Resists; Substrates; Wires;
Conference_Titel :
Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th
Conference_Location :
Singapore
Print_ISBN :
978-1-4577-1983-7
Electronic_ISBN :
978-1-4577-1981-3
DOI :
10.1109/EPTC.2011.6184448