Title :
A concurrent two-step flash analogue-to-digital converter architecture
Author :
Vital, J.C. ; Franca, J.E.
Author_Institution :
Instituto Superior Tecnico
Keywords :
Analog integrated circuits; Capacitors; Computer architecture; Delay; Feedback loop; Phased arrays; Recycling; Sampling methods; Throughput; Voltage;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
IEEE
Print_ISBN :
0-7803-1281-3
