Development of Via in Mold (ViM) for embedded wafer level package (EWMLP)

In this paper, a Via in Mold (ViM) interconnects were developed for embedded wafer level package (EMWLP) to enable 3D application. ViM interconnects are essentially plated blind vias drilled into the mold compound substrate. The two key processes required for ViM development are laser drilling of blind vias and Cu seed layer deposition. Mold compound is a composite material made up of epoxy resin and filler particles. The non-uniform distribution of filler particles in the matrix will make consistent laser drilling results difficult to achieve. Laser drilling process parameters were optimized such that the drilling depth is stopped at the Cu metallization pads without damaging the metallization. The sidewall roughness of laser drilled vias makes it difficult for physical vapor deposition process to achieve a conformal seed layer. In order to overcome issues with rough vias sidewall, an electroless Cu plating process was adopted. Electroless Cu plating process was optimized to deposit a conformal Cu seed layer along the sidewall. Electrolytic Cu plating was used to build up the electroless Cu seed layer to the desired thickness for electrical connection. A test vehicle which consists of 50 via-chains was fabricated using the optimized process parameters. The via-chains electrical resistance was measured to extract the resistance of a single ViM. From the electrical resistance measurement, the resistance for a single ViM is ~0.02 Ω.