A comprehensive approach to the design of digit-serial modified booth multipliers

Presents a novel approach to the design and gate-level implementation of digit-serial modified Booth multipliers. The proposed approach is based on the decomposition of the multiplicand and the multiplier each into a unique set of D radix-2^D components, where D represents the digit-size being used. This permits the desired final product to be formed in terms of the decomposed components of the multiplicand and the multiplier. Empirical results are presented to show the efficiency of the resulting implementations using Actel 1.2 μ FPGA technology, where the efficiency is quantified by the throughput per unit area. It is shown that the maximum efficiency is achieved by using digit-serial multipliers operating between the full bit-serial and the full bit-parallel mode