Implementation and performance evaluation of cellular array multipliers using FPGAs

The design of fast and efficient multipliers is imperative, because of its various applications in many areas of science and engineering. In the light of VLSI technology, it is important for computer hardware designers to be aware of the choices available to them, in selecting an efficient algorithm for their application. High speed cellular-array multipliers have been the logical and affordable improvement compared to the serial-parallel designs. The authors present a detailed discussion on the development of these multiplier algorithms and their FPGA implementations. The various issues involved in the design process are highlighted. The cost-performance comparison of the various cellular array multipliers and a discussion on the design methodology is also presented