Optimization of IQ mismatch test

An increased emphasis on SIP (System In Package) can be seen in the market due to its advantage in performance, form factor, cost and time to market. The yield of SIP is dependent on the yield of individual component. To avoid the high costs of a defect in a SIP, it is necessary to carry out full test coverage in wafer level to achieve "known-good-dies". To ensure optimum test yield, it is important to ensure that calibrations are duly carried out for critical tests. IQ test is one of the critical tests in RF / mixed signal devices as baseband IQ signals have great impact on the device performance. To improve the yield and measurement accuracy of IQ test, it is important that I and Q signals are properly optimized. This paper attempts to illustrate the effect of IQ mismatch and methods to calibrate out the mismatch due to instruments and test fixture.