Visualizing test information: A novel approach for improving testability

As circuit size increases, the difficulty of generating test sets with acceptable fault coverage within useful time limits increases by a non-polynomial factor. Information from test generation programs provides a basis for circuit modification targeting increased fault coverage in reduced time with fewer test vectors. In its raw form, this information is difficult, if not impossible, to comprehend. This research employs visualization techniques to create an interactive environment for rapid analysis of this multidimensional data. Test generation information is visually associated with individual and identifiable circuit components. Additionally, dependency information is illustrated. Hypotheses about relationships between fault coverage statistics and the circuit can be explored and used as a starting point for improving overall testability