Analysis of trap mechanisms responsible for Random Telegraph Noise and erratic programming on sub-50nm floating gate flash memories

In this work we present a systematic investigation concerning the correlation of Random Telegraph Noise (RTN) with erratic bits in sub-50 nm floating gate NAND memory cells. Both effects are compared with respect to their implication in reliability and cell operation parameters of sub-50 nm flash devices. Related measurements were performed on a test chip with large floating gate cell arrays in NAND architecture. The analysis methods for both effects are presented comparing the magnitude and cycling stress dependency in detail. Additionally, two integration concepts with different memory cell sidewall oxidation approaches are discussed effecting differently the RTN and erratic programming behavior. Based on the characterization results we conclude that both effects are originating from different trap mechanisms. Possible explanations for the different trap mechanisms and locations are discussed.