Title :
CMOS bridges and resistive transistor faults: IDDQ versus delay effects
Author :
Vierhaus, H.T. ; Meyer, W. ; Gläser, U.
Author_Institution :
German Nat. Res. Center for Comput. Sci., Syst. Design Technol. Inst., St. Augustin, Germany
Abstract :
Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing
Keywords :
CMOS integrated circuits; delays; electric current measurement; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS bridges; IDDQ; bridging faults; delay effects; delay fault testing; detectability; fault coverage; resistive transistor faults; simulations; static overcurrent testing; static stuck-at fault model; stuck-on faults; stuck-open faults; timing resolutions; Analytical models; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Delay; Electrical fault detection; Fault detection; Semiconductor device modeling; Timing;
Conference_Titel :
Test Conference, 1993. Proceedings., International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-1430-1
DOI :
10.1109/TEST.1993.470715
