Title :
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder
Author :
Chen, Yi-Hau ; Chuang, Tzu-Der ; Chen, Yu-Han ; Tsai, Chen-Han ; Chen, Liang-Gee
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
High Definition (HD) H.264/AVC video compression is the emerging necessity on nowadays home entertainment environment and so on. However, Although B-frame coding scheme provides better quality, only P-frame encoders are presented due to too high complexity and memory requirement. In this paper, a frame-parallel encoding scheme based on B-frame´s data independency is proposed. It can largely reduce the system memory bandwidth and improve the processing capability. Then, the proposed IME and FME scheduling can further enhance the hardware utilization for frame-parallel scheme. Finally, a case study is given to show that the proposed scheme can largely reduce 66% system bandwidth compared to direct implementation from previous P-frame encoder.
Keywords :
computational complexity; data compression; high definition video; scheduling; video coding; B-frame coding scheme; FME scheduling; IME scheduling; P-frame encoders; frame-parallel design strategy; hardware utilization; high definition B-frame H.264-AVC encoder; system memory bandwidth; video compression; Automatic voltage control; Bandwidth; Encoding; Frequency; Hardware; High definition video; Parallel processing; Pipelines; Scheduling; Strontium;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541346