Embedded component substrates moving forward

Embedded die substrates (EDS) and embedded passives substrates (EPS) have been developed and promoted for many years already but still have to find their way into the market place. The adoption has been slow for several reasons: lack of a business model, design soft ware, test strategy and capability, standards and substrate yield. Printed wiring boards (PWB) have long adopted passives in their applications but they are typically formed passives i.e. capacitors, resistors and inductors formed during the board manufacturing process employing adapted materials to provide higher dielectric constants (D_k) or resistive values (□). Substrates are significantly smaller in area than PWBs and the materials still have rather low D_k/□ values. Further the manufacturing processes involved do not afford tight tolerance values. Hence, substrates favor the use of discretes and known good (KGD) flip chip dies (FC). It seems that nearly every substrate manufacturer has developed they own methodology and employed their specific material set to develop this technology which circumvents standardization in the near term. A large volume adaptor will be required to drive standardization either thru a standards organization or de-facto thru large volume sourced from several suppliers. The yield situation of substrates can be addressed by design i.e. employ less aggressive designs which result in higher yields and avoid the costly scrap of KGDs. Of course substrate suppliers are not accustomed to handling die (die banks, electrostatic protection, thin die or small discrete handling, etc.) ASE is well positioned to deal with these issues being a substrate manufacturer as well as the largest assembly subcon.