Development of Copper Via Exposure by two steps process

This paper will present the work developed for Copper Via Exposure to enable further processing on the backside of the wafer; re-distribution layer (RDL), passivation coating, etc. It important to achieve a planarized surface, as uneven silicon surface or copper bump would cause more complicated issues to the subsequent processes. Some critical challenges in Copper Via Exposure includes the simultaneous grinding of brittle silicon and ductile copper that is embedded inside the silicon wafer and the control of the copper migration throughout the wafer. By using the two steps method, the surface planarity between the copper TSV and silicon substrate is in the range of 100 ~ 300nm. In addition, there is no sign of copper migration within the silicon substrate as shown by the result of the Auger analysis.