TSV via-last: Optimization of multilayer dielectric stack etching

3D Through-silicon via (TSV) has been acknowledged as one of the future chip design technologies. In this paper, via last after Back End Of Line (BEOL) and before bonding, CMOS wafer with 18 layers of multilayer dielectric dry etching prior to deep silicon etching is presented. TSV Via dry etching of CMOS wafer of 40 μm, 8.5 μm thick multilayer dielectric which consists of several dielectric materials such as low k, SiCOH, Si3N4, HARP and USG will be discussed. Three masking schemes and their respective challenges are reported in the paper. Using 5.9 μm photo resist and optimum etching recipe, we have demonstrated multilayer dielectric stack dry etching resulting in straight smooth via required by subsequent TSV etching into Si substrates.