DocumentCode
1828964
Title
A 50-Gbit/s 1:4 demultiplexer IC in InP-based HEMT technology
Author
Kano, H. ; Suzuki, T. ; Yamaura, S. ; Nakasha, Y. ; Sawada, K. ; Takahashi, T. ; Makiyama, K. ; Hirose, T. ; Watanabe, Y.
Author_Institution
Fujitsu Labs. Ltd., Atsugi, Japan
Volume
1
fYear
2002
fDate
2-7 June 2002
Firstpage
75
Abstract
We have developed a 50-Gb/s 1:4 demultiplexer (DEMUX) integrated circuit with a wide phase margin of 108 degrees in 0.13-/spl mu/m InP-based HEMT technology. To increase the phase margin, we designed the data and clock distribution with the aim of achieving high symmetry and eliminating multiple reflections. The measured performance of the fabricated 1:4 DEMUX was suitable for practical use in 50-Gbit/s-class applications.
Keywords
HEMT integrated circuits; III-V semiconductors; clocks; demultiplexing equipment; field effect logic circuits; indium compounds; 0.13 micron; 50 Gbit/s; HEMT technology; InP; clock distribution; data distribution; demultiplexer IC; multiple reflections; phase margin; source-coupled FET logic; symmetry; Circuits; Clocks; Degradation; Delay; Flip-flops; HEMTs; Monitoring; Optical reflection; Timing; Tree data structures;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Symposium Digest, 2002 IEEE MTT-S International
Conference_Location
Seattle, WA, USA
ISSN
0149-645X
Print_ISBN
0-7803-7239-5
Type
conf
DOI
10.1109/MWSYM.2002.1011562
Filename
1011562
Link To Document