Title :
Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio
Author_Institution :
IRISA, Rennes, France
Abstract :
Sectored caches have been used for many years in order to reconcile low tag array size and small or medium block size. In a sectored cache, a single address tag is associated with a sector consisting on several cache lines, while validity, dirty and coherency tags are associated with each of the inner cache lines. Usually in a cache, a cache line location is statically linked to one and only one address tag word location. In the decoupled sectored cache introduced in the paper, this monolithic association is broken; the address tag location associated with a cache line location is dynamically chosen at fetch time among several possible locations. The tag volume on a decoupled sectored cache is in the same range as the tag volume in a traditional sectored cache; but the hit ratio on a decoupled sectored cache is very close to the hit ratio on a non-sectored cache. A decoupled sectored cache will allow the same level of performance as a non-sectored cache, but at a significantly lower hardware cost
Keywords :
buffer storage; memory architecture; performance evaluation; address tag; address tag location; decoupled sectored cache; hit ratio; low miss ratio; low tag implementation cost; performance; sectored caches; Costs; Frequency; Hardware; Microprocessors; Technical Activities Guide -TAG;
Conference_Titel :
Computer Architecture, 1994., Proceedings the 21st Annual International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-8186-5510-0
DOI :
10.1109/ISCA.1994.288133