• DocumentCode
    1829376
  • Title

    METRO: a router architecture for high-performance, short-haul routing networks

  • Author

    DeHon, André ; Chong, Frederic ; Becker, Matthew ; Egozy, Eran ; Minsky, Henry ; Peretz, Samuel ; Knight, Thomas F., Jr.

  • Author_Institution
    Artificial Intelligence Lab., MIT, Cambridge, MA, USA
  • fYear
    1994
  • fDate
    18-21 Apr 1994
  • Firstpage
    266
  • Lastpage
    277
  • Abstract
    The Multipath Enhanced Transit Router Organization (METRO) is a flexible routing architecture for high-performance, tightly-coupled, multiprocessors and routing hubs. A METRO router is a dilated crossbar routing component supporting half-duplex bidirectional, pipelined, circuit-switched connections. Each METRO router is self-routing and supports dynamic message traffic. The routers works in conjunction with source-responsible network interfaces to achieve reliable end-to-end data transmission in the presence of heavy network congestion and dynamic faults. METRO separates the fundamental architectural characteristics from implementation parameters. Simplicity of routing function coupled with freedom in the implementation parameters allows METRO implementations to fully exploit available technology to achieve low-latency and high-bandwidth. We illustrate the effects of this implementation freedom by summarizing the performance which various METRO configurations can extract from some modern CMOS technologies. METROJR-ORBIT, a minimal instance of the METRO architecture constructed in a 1.2 μ gate-array technology, is included
  • Keywords
    circuit switching; computer networks; parallel architectures; pipeline processing; telecommunication network routing; telecommunication traffic; METRO; METROJR-ORBIT; Multipath Enhanced Transit Router Organization; dynamic message traffic support; end-to-end data transmission; flexible routing architecture; gate array; half duplex bidirectional pipelined circuit-switched connections; network congestion; short haul routing networks; source responsible network interfaces; Artificial intelligence; CMOS technology; Circuit faults; Contracts; Couplings; Data communication; Delay; Laboratories; Network interfaces; Routing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 1994., Proceedings the 21st Annual International Symposium on
  • Conference_Location
    Chicago, IL
  • Print_ISBN
    0-8186-5510-0
  • Type

    conf

  • DOI
    10.1109/ISCA.1994.288143
  • Filename
    288143