• DocumentCode
    1829436
  • Title

    Advanced processes and materials for temporary wafer bonding

  • Author

    McCutcheon, Jeremy W. ; Blumenshine, Debbie L. ; Lee, Alvin

  • Author_Institution
    Brewer Sci., Inc., Rolla, MO, USA
  • fYear
    2011
  • fDate
    7-9 Dec. 2011
  • Firstpage
    744
  • Lastpage
    746
  • Abstract
    Advances in semiconductor technology are still being made in traditional lithography techniques, however, the industry is beginning to look into alternative ways to reduce size and form factor while increasing performance at the same time. One such pathway is to stack various functional chips vertically. To do this, the base substrate must be very thin to allow for electrical connections, termed through-silicon-vias, to pass through. Once the substrate is thinned, it is very fragile and must be supported, either in a built up package or by being attached to a temporary carrier or handle wafer. The former is a permanent chip-to-wafer bonding, while the latter is a temporary wafer bonding. Both methods play roles in enabling chip stacking for the creation of three-dimensional integrated circuits as well as many other advanced micro devices such as MEMS. The purpose of this research was to develop a specialized method of temporary wafer bonding to enable the transfer of fragile device wafers from one carrier to another to allow processing on both sides of the device wafer in multiple sequences. The work utilized ZoneBOND™ technology from Brewer Science, Inc. to create multiple zones on carrier substrates using advanced materials with different solubilities. In this process, a simulated device wafer was temporarily bonded to a first carrier using one adhesive. Then a second carrier was bonded to the opposite side of the device wafer using a different adhesive. Then the stack was exposed to a solvent that selectively softened the adhesive on the outer zone of the first carrier. This carrier was then removed, thus transferring the device wafer from the first to the second carrier.
  • Keywords
    lithography; three-dimensional integrated circuits; wafer bonding; MEMS; ZoneBOND technology; carrier substrate; carrier wafer; chip stacking; chip-to-wafer bonding; electrical connection; fragile device wafer; functional chip; handle wafer; lithography technique; microdevice; semiconductor technology; temporary wafer bonding; three-dimensional integrated circuit; through-silicon-vias; Bonding; Industries; Silicon; Solvents; Substrates; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference (EPTC), 2011 IEEE 13th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4577-1983-7
  • Electronic_ISBN
    978-1-4577-1981-3
  • Type

    conf

  • DOI
    10.1109/EPTC.2011.6184518
  • Filename
    6184518