DocumentCode
1829476
Title
Code Annealing and the Suppressing Effect of the Cyclically Lifted LDPC Code Ensemble
Author
Wang, Chih-Chun
Author_Institution
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN
fYear
2006
fDate
22-26 Oct. 2006
Firstpage
86
Lastpage
90
Abstract
Code annealing, a new method of designing good codes of short block length, is proposed, which is then concatenated with cyclic lifting to create finite codes of low frame error rate (FER) error floors without performance outliers. The stopping set analysis is performed on the cyclically lifted code ensemble assuming uniformly random lifting sequences, and the suppressing effect/weight of the cyclic lifting is identified for the first time, based on which the ensemble FER error floor can be analytically determined and a scaling law is derived. BoUe the first-order and high-order suppressing effects are discussed and quantified by different methods including the explicit expression, an algorithmic upper bound, and an algebraic lower bound. The mismatch between the suppressing weight and the stopping distances explains the dramatic performance discrepancy among different cyclically lifted codes when the underlying base codes have degree 2 variable nodes or not. For the former case, a degree augmentation method is further introduced to mitigate this metric mismatch, and a systematic method of constructing irregular codes of low FER error floors is presented. Both regular and irregular codes of very low FER error floors are reported, for which the improvement factor ranges from 106 - 104 when compared to the classic graph-based code ensembles
Keywords
concatenated codes; error statistics; graph theory; parity check codes; random sequences; FER; algorithmic upper bound; code annealing; concatenated codes; cyclic lifting; cyclically lifted LDPC code ensemble; degree augmentation method; frame error rate; graph-based code ensembles; stopping set analysis; uniformly random lifting sequences; Algorithm design and analysis; Annealing; Conferences; Design engineering; Design optimization; Error analysis; Information theory; Parity check codes; Performance analysis; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory Workshop, 2006. ITW '06 Chengdu. IEEE
Conference_Location
Chengdu
Print_ISBN
1-4244-0067-8
Electronic_ISBN
1-4244-0068-6
Type
conf
DOI
10.1109/ITW2.2006.323762
Filename
4119260
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