Quasi-adiabatic 2×2 Barrel Shifter

Demands for low power electronics have motivated designers to explore new approaches to VLSI circuits. The classical approaches of reducing energy dissipation in conventional CMOS circuits include reducing the supply voltages, node capacitances, and switching frequencies. Energy-recovery circuitry, on the other hand, is a new promising approach to the design of VLSI circuits with very low energy dissipation. Such circuits achieve low energy dissipation by restricting current to flow across devices with very low voltage drop and by recycling the energy stored on their capacitors. This paper analyzes the performance of Pass Transistor Adiabatic Logic (PAL) against that of static CMOS. A standard 2X2 Barrel Shifter is used as the benchmark circuit for comparison due to its modular design. The analysis is carried out in cadence design environment using 180nm technology using cell based design approach. The simulation is done at various operating voltages, frequencies, and load capacitances for each circuit family and technological node.