9.5 Gbit/s 20 channel 1∶8 DEMUX for a coherent optical receiver DSPU ASIC input interface

Author

Herath, Vijitha R. ; Adamczyk, Olaf ; Peveling, Ralf ; Wödehoff, Christian ; Noé, Reinhold

Author_Institution

Univ. of Peradeniya, Peradeniya, Sri Lanka

fYear

2009

fDate

28-31 Dec. 2009

Firstpage

312

Lastpage

316

Abstract

This paper presents the design of an input interface to a CMOS DSPU of an optical coherent QPSK with polarization multiplex receiver. The interface consists of a 20 channel 1:8 DEMUX. Source Coupled FET logic (SCFL) and CMOS logic were used in the design. The interface converts 10 Gbit/s input data rate to 1.25 Gbit/s at the output. The interface gives an open eye diagram at the output up to 9.5 Gbit/s input data rate. The system consumes 7.9 mW/channel.Gb/s. 130 nm bulk CMOS technology was used in the design.

Keywords

CMOS logic circuits; application specific integrated circuits; demultiplexing; electromagnetic wave polarisation; field effect transistors; optical receivers; quadrature phase shift keying; 20 channel 1:8 DEMUX; CMOS DSPU; CMOS logic; DSPU ASIC input interface; coherent optical receiver; open eye diagram; optical coherent QPSK; polarization multiplex receiver; source coupled FET logic; Application specific integrated circuits; CMOS logic circuits; CMOS technology; FETs; Logic design; Optical design; Optical polarization; Optical receivers; Quadrature phase shift keying; Signal analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial and Information Systems (ICIIS), 2009 International Conference on

Conference_Location

Sri Lanka

Print_ISBN

978-1-4244-4836-4

Electronic_ISBN

978-1-4244-4837-1

Type

conf

DOI

10.1109/ICIINFS.2009.5429846

Filename

5429846