• DocumentCode
    1829788
  • Title

    Hardware Implementation of Fast Division Algorithm for GF(2m)

  • Author

    Kang, Min-Sup ; Lee, Kwang-Ho

  • Author_Institution
    Dept. of Comput. Eng., Anyang Univ.
  • Volume
    1
  • fYear
    2006
  • fDate
    20-22 Feb. 2006
  • Firstpage
    117
  • Lastpage
    119
  • Abstract
    This paper proposes a fast division algorithm and architecture for GF(2m) using standard basis representation. The algorithm implemented is based on the binary extended GCD algorithm. We have shown that the computation speed of the proposed algorithm is significantly improved than the previous approach. The design can operate at a clock frequency of 80 MHz on Xilinx-VirtexII XC2V8000 FPGA device
  • Keywords
    field programmable gate arrays; public key cryptography; 80 MHz; GF(2m); Xilinx-VirtexII XC2V8000 FPGA device; basis representation; binary extended GCD algorithm; clock frequency; fast division algorithm; hardware implementation; Clocks; Computer architecture; Field programmable gate arrays; Frequency; Hardware; Binary extended GCD algorithm; Euclidean algorithm; FPGA; Finite field arithmetic; modular division;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Communication Technology, 2006. ICACT 2006. The 8th International Conference
  • Conference_Location
    Phoenix Park
  • Print_ISBN
    89-5519-129-4
  • Type

    conf

  • DOI
    10.1109/ICACT.2006.205932
  • Filename
    1625537
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1829788