Title :
A channelless layout for multilevel synthesis with compiled cells
Author :
Saucier, G. ; Leveugle, R. ; Abouzeid, P.
Author_Institution :
Inst. Nat. Polytech. de Grenoble, France
Abstract :
A novel method for optimized multilevel synthesis of CMOS circuitry in terms of compiled cells is presented. A compiled cell is the implementation on silicon of a lexicographical factorized Boolean expression. How a compiled cell is obtained automatically from the Boolean expression (layout synthesis) is recalled, and the rewriting of Boolean functions in terms of compiled cells is addressed. This approach leads to a dense and regular layout by abutment of compiled cells. The wiring channels are thus suppressed
Keywords :
Boolean functions; CMOS integrated circuits; circuit layout; wiring; Boolean functions; CMOS; abutment; channelless layout; compiled cells; layout synthesis; lexicographical factorized Boolean expression; multilevel synthesis; regular layout; wiring channels; Boolean functions; Integrated circuit layout; Kernel; Silicon; Wiring;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63323
