A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding

Motion compensation (MC) is the computation bottleneck in H.264/AVC decoding and it dominates DRAM traffic. To alleviate computation loading, we employ two interpolation engines and fully utilize them in both P and B slices. Compared with a traditional separate 1-D interpolation engine, our proposed approach can reduce 79% of average computation latency. To reduce memory traffic, we propose a High Efficiency Reference Frame Pre-Fetch Scheme (HERPS) that saves 91% of multiple reference frame memory access cycles by rearranging access patterns. The overall design costs 117 K gates when running at 200 MHz and supports up to the QFHD (3840times2160) at 30 frames per second (fps) using a 128-bit DRAM memory system.