Title :
A robust high voltage Si LDMOS model extraction process to achieve first pass linear RFIC amplifier design success
Author :
Pla, J.A. ; Bridges, D.
Author_Institution :
Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
Abstract :
A robust model extraction procedure was developed for a high voltage Si LDMOS RFIC process to achieve first pass linear RFIC amplifier design success. The model extraction process utilizes pulsed isothermal small-signal S-parameter measurements and extracted large-signal root models at three different temperatures to extract model parameters for Motorola´s Electro-Thermal (MET) FET analytical model. Large-signal model validation was performed against loadpull measurements under 1-tone and 2-tone stimuli. Also, the models were developed into a design kit within Agilent/sup R/ EEsof/sup R/´s ADS/sup R/ (Advanced Design System) to design a wide-band 30 Watt power amplifier IC which achieved first pass design success.
Keywords :
MOS analogue integrated circuits; S-parameters; UHF integrated circuits; UHF power amplifiers; integrated circuit design; integrated circuit modelling; power integrated circuits; wideband amplifiers; 1-tone stimuli; 2-tone stimuli; 30 W; Agilent EEsof Advanced Design System; Motorola electro-thermal FET analytical model; first pass linear RFIC amplifier design success; high voltage LDMOS RFIC process; large-signal model validation; large-signal root models; loadpull measurements; pulsed isothermal small-signal S-parameter measurements; robust high voltage Si LDMOS model extraction process; wide-band power amplifier IC design; Integrated circuit modeling; Isothermal processes; Power system modeling; Pulse amplifiers; Pulse measurements; Radiofrequency integrated circuits; Robustness; Scattering parameters; Temperature; Voltage;
Conference_Titel :
Microwave Symposium Digest, 2002 IEEE MTT-S International
Conference_Location :
Seattle, WA, USA
Print_ISBN :
0-7803-7239-5
DOI :
10.1109/MWSYM.2002.1011607
