A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

Author

Hashida, Toshiyuki ; Tomita, Yasumoto ; Ogata, Y. ; Suzuki, Kenji ; Suzuki, Satoshi ; Nakao, Tomoki ; Terao, Yutaka ; Honda, Shogo ; Sakabayashi, S. ; Nishiyama, R. ; Konmoto, Akihiko ; Ozeki, Yasuyuki ; Adachi, H. ; Yamaguchi, Hitoshi ; Koyanagi, Yoshio

Author_Institution

Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of skew and jitter. The transceiver occupies 0.55 mm² and consumes 609.9 mW of power from a 0.9-V supply.

Keywords

CMOS analogue integrated circuits; MMIC frequency convertors; clock distribution networks; decision feedback equalisers; delay lock loops; field effect MMIC; frequency multipliers; radio transceivers; 1-tap DFE; bit rate 36 Gbit/s; clock-delivery power; continuous-time linear equalizer; delay-locked loop; frequency 9 GHz; frequency doublers; jitter; multiphase half-rate clock signals; power 609.9 mW; quarter-rate clock distribution; size 20 nm; skew; transceiver front-ends; voltage 0.9 V; CMOS integrated circuits; Clocks; Decision feedback equalizers; Delays; Jitter; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858359

Filename

6858359