Spiral inductor performance in deep-submicron bulk-CMOS with copper interconnects

Author

Kuhn, W.B. ; Orsborn, A.W. ; Peterson, M.C. ; Kythakyapuzha, S.R. ; Hussein, A.I. ; Jun Zhang ; Jianming Li ; Shumaker, E.A. ; Nair, N.C.

Author_Institution

Dept. of Electr. & Comput. Eng., Kansas State Univ., Manhattan, KS, USA

Volume

1

fYear

2002

fDate

2-7 June 2002

Firstpage

301

Abstract

This paper reviews design considerations for spiral inductors in bulk CMOS and reports investigations carried out in a commercial 0.18 /spl mu/m process using 6-layer copper metalization. Quality factors of approximately 8 are measured for 10 nH spirals operating between 1 and 2 GHz. Comparisons of Q and self-resonant frequency are provided for a variety of construction variables including with/without a patterned ground shield, metal-6 only versus stacking layers 3 thru 6, dense versus sparse vias, wide versus narrow traces, and with/without metal-fill.

Keywords

CMOS integrated circuits; Q-factor; copper; frequency response; inductors; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; 0.18 micron; 1 GHz; 2 GHz; Cu; Q-factor; bulk CMOS processes; commercial fabrication process; copper interconnects; dense vias; device construction variables; metal-6 layer; metal-fill; narrow traces; patterned ground shield; quality factor; self-resonant frequency; six-layer copper metalization; sparse vias; spiral inductors; stacked layers; via density; wide traces; CMOS process; Capacitance; Copper; Eddy currents; Frequency; Inductance; Inductors; Q factor; Spirals; Stacking;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest, 2002 IEEE MTT-S International

Conference_Location

Seattle, WA, USA

ISSN

0149-645X

Print_ISBN

0-7803-7239-5

Type

conf

DOI

10.1109/MWSYM.2002.1011617

Filename

1011617