Title :
A 40-Gb/s serial link transceiver in 28-nm CMOS technology
Author :
E-Hung Chen ; Hossain, M. ; Leibowitz, Brian ; Navid, Reza ; Jihong Ren ; Chou, Alvin ; Daly, Barry ; Aleksic, Marko ; Su, Bo-Rung ; Li, Sinan ; Shirasgaonkar, Makarand ; Heaton, Fred ; Zerbe, Jared ; Eble, John
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
A SerDes operating at 40 Gb/s optimized for chip-to-chip communication is presented. Equalization consists of 2-tap feed-forward equalizers (FFE) in both transmitter and receiver, a 3-stage continuous-time linear equalizer (CTLE) and discrete-time equalizers including a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled-FFE in the receiver. The SerDes is realized in 28-nm CMOS technology with 23.2 mW/Gb/s power efficiency at 40 Gb/s.
Keywords :
CMOS analogue integrated circuits; decision feedback equalisers; transceivers; 17-tap DFE; 17-tap decision feedback equalizer; 3-stage CTLE; 3-stage continuous-time linear equalizer; 3-tap sampled-FFE; CMOS technology; SerDes; bit rate 40 Gbit/s; chip-to-chip communication; discrete-time equalizer; feed-forward equalizers; power efficiency; serial link transceiver; size 28 nm; CMOS integrated circuits; Decision feedback equalizers; Electrostatic discharges; Phase locked loops; Receivers; Transceivers;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858361
