A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering

Author

Hossain, M. ; E-Hung Chen ; Navid, Reza ; Leibowitz, Brian ; Chou, Alvin ; Li, Sinan ; Park, M.J. ; Jihong Ren ; Daly, Barry ; Su, Bo-Rung ; Shirasgaonkar, Makarand ; Heaton, Fred ; Zerbe, Jared ; Eble, John

Author_Institution

Rambus Inc., Sunnyvale, CA, USA

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 4×40 Gb/s collaborative digital CDR is implemented in 28nm CMOS. The CDR is capable of recovering a low jitter clock from a partially-equalized or un-equalized eye by using a phase detection scheme that inherently filters out ISI edges. The CDR uses split feedback that simultaneously allows wider bandwidth and lower recovered clock jitter. A shared frequency tracking is also introduced that results in lower periodic jitter. Combining these techniques the CDR recovers a 10GHz clock from an eye containing 0.8UIpp DDJ and still achieves 1-10 MHz of tracking bandwidth while adding <; 300fs of jitter. Per lane CDR occupies only .06 mm² and consumes 175 mW.

Keywords

CMOS integrated circuits; clock and data recovery circuits; phase detectors; synchronisation; CMOS; bandwidth 1 MHz to 10 MHz; collaborative digital clock and data recovery circuits; data dependent jitter filtering; low jitter clock; partially-equalized eye; phase detection scheme; power 175 mW; quad-lane CDR; shared frequency tracking; size 28 nm; split feedback; un-equalized eye; Bandwidth; Clocks; Filtering; Frequency measurement; Jitter; Phase locked loops; Phase measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858362

Filename

6858362