An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range

Author

Bannon, Alan ; Hurrell, Christopher Peter ; Hummerston, Derek ; Lyden, Colin

Author_Institution

Analog Devices, Cork, Ireland

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

This paper presents an 18 bit 5 MS/s SAR ADC. It has a dynamic range of 100.2 dB, SNR of 99 dB, INL of ±2 ppm and DNL of ±0.4 ppm. It has currently the lowest noise floor of any monolithic Nyquist converter relative to the full scale input (21.9 nV/√Hz, ±5V full scale) known to the author, all of this is achieved with an ADC core power of 30.52 mW giving a Schreier figure of merit of 179.3 dB [1]. Architectural choices such as the use of a residue amplifier are outlined that enable the high sample rate, low noise and power efficiency. The design is implemented on 0.18 μm CMOS with MIM capacitors and both 1.8 V and 5 V MOS devices. An LVDS interface is used to transfer the ADC result off chip.

Keywords

CMOS integrated circuits; MIM devices; MIS devices; amplifiers; analogue-digital conversion; capacitors; thermal noise; CMOS; LVDS interface; MIM capacitors; MOS devices; SAR ADC; Schreier figure of merit; dynamic range; monolithic Nyquist converter; power 30.52 mW; size 0.18 mum; voltage 1.8 V to 5 V; word length 18 bit; Bandwidth; CMOS integrated circuits; Capacitors; Dynamic range; Floors; Signal to noise ratio; ADC; SAR; residue amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858371

Filename

6858371