Power-aware topology optimization for networks-on-chips

The choice of a network topology for a networks- on-chip based application significantly impacts its power consumption. In this paper, we propose a new methodology to reduce the total power consumption of the global router-to-router links by selecting the optimal network topology. The proposed methodology merges three mapping approaches: network partitioning, standard topology mapping, and long-range insertion. Analytical power models for global links are studied at different levels of abstraction. The proposed methodology is validated through a case study. Experimental results show the power consumption improvement compared to related work.