A robust alternate repeater technique for high performance busses in the multi-core era

This paper describes an alternate repeater insertion technique that uses correct-by-construction polarities to reduce worst-case miller coupling factor (MCF) across any multiple segmented portion of a repeated bus. Simple static CMOS circuits with nominal p-n skews allow drop-in replacement while maintaining robust operation. For the same repeater area, number and position of repeaters of conventional busses, this technique simultaneously reduces delay by 15%, energy by 29% and peak current by 12% for 2-8 mm on-chip busses in 1.2 V, 65 nm CMOS. Under equal delay constraints, the proposed technique reduces worst-case energy and peak current by 39% and 36%, respectively. The technique easily extends to shared busses for multi-core designs and shows a 41% improvement in energy-efficiency for a 10 mm 5 GHz multi-cycle on-chip core-to- core bus.