A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier

A hybrid dynamic amplifier is proposed which combines the desirable features of a dynamic amplifier and a class AB amplifier. This technique allows us to achieve a power efficient high resolution pipeline ADC. A proof of concept pipelined ADC in a 0.18 μm CMOS process achieves 74.2 dB SNDR, 87 dB SFDR and 85 dB THD at 30 MS/s. The pipeline ADC consumes 6 mW from a 1.3 V supply and occupies 3.06 mm². The ADC achieves a FoM of 48 fJ/CS without any form of calibration.