• DocumentCode
    1830646
  • Title

    Acceleration of Generalized Minimum Aberration Designs of Hadamard Matrices on Graphics Processing Units

  • Author

    Calhoun, Jon ; Graham, Josh ; Zhou, Hong ; Jiang, Hai

  • Author_Institution
    Dept. of Comput. Sci., Arkansas State Univ., Jonesboro, AR, USA
  • fYear
    2012
  • fDate
    25-27 June 2012
  • Firstpage
    1294
  • Lastpage
    1300
  • Abstract
    The process of applying generalized minimum aberration criteria (GMAC) to non-regular fractional factorial designs is extremely computationally intensive. Constructing and ranking all designs can take hours if not days; therefore, exploitation of the massively parallel nature of modern graphics processing units (GPUs) are used to perform the task. The computation is not just ported to the GPU, but is implemented as to optimize performance based upon the modern GPU architecture. Optimizations include using bit operations and table lookups to reduce the number of addition and multiplication operations performed. Tables are housed in GPU constant memory with almost no latency for access. Using a statistical proof from previous research reduces the memory required for the calculation. Optimizations regarding memory storage and transfer in NVIDIA´s Compute Unified Device Architecture (CUDA) are also explored, as well as advance features such as streams and multiple GPUs. Experimental results have demonstrated the effectiveness of the proposed approach.
  • Keywords
    Hadamard matrices; graphics processing units; mathematics computing; optimisation; parallel algorithms; parallel architectures; statistical analysis; table lookup; CUDA; GPU architecture; GPU constant memory; Hadamard matrices; NVIDIA; addition operations; bit operations; compute unified device architecture; generalized minimum aberration design; graphic processing units; memory requirement; memory storage optimization; multiplication operations; nonregular fractional factorial designs; performance optimize; statistical proof; table lookups; Error correction; Error correction codes; Graphics processing unit; Indexes; Kernel; Memory management; Sorting; Compute Unified Device Architecture; Generalized Minimum Aberration Criteria; Graphics Processing Unit; Hadamard Matrices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on
  • Conference_Location
    Liverpool
  • Print_ISBN
    978-1-4673-2164-8
  • Type

    conf

  • DOI
    10.1109/HPCC.2012.191
  • Filename
    6332327