A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS

A highly digital quadrature clock generator using a digital DLL that employs a digital loop filter and digitally-calibrated replica-based regulator is presented. The proposed DLL combines the advantages of both analog and digital loop-filters of conventional architectures to implement a wide-range, energy efficient, highly digital, and high performance quadrature clock generator. To suppress supply-noise, we propose an LDO that combines fast/slow paths with a replica-load to achieve better than 20dB rejection with small area and low power. Fabricated in Intel´s 14nm CMOS process, the proposed digital DLL operates over a wide range of output frequencies (2GHz-to-7.5GHz). At 7GHz, it achieves 176fs_rms/2.7ps_pp long-term jitter while consuming 4.4mW. The DLL is 4X smaller than state-of-the art designs and occupies an active area of 0.0024mm².