A monolithically-integrated chip-to-chip optical link in bulk CMOS

Author

Sun, Chao ; Georgas, M. ; Orcutt, Jason S. ; Moss, B.R. ; Chen, Yu-Hui ; Shainline, Jeffrey ; Wade, Mark ; Mehta, Karan ; Nammari, Kareem ; Timurdogan, Erman ; Miller, David ; Tehar-Zahav, Ofer ; Sternberg, Zvi ; Leu, J.C. ; Chong, Johanna ; Bafrali, Reha

Author_Institution

Massachusetts Inst. of Technol., Cambridge, MA, USA

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A silicon-photonic link is monolithically-integrated in a bulk CMOS process for the first time. Deep-trench isolation enables polySi waveguide integration. PolySi resonant detectors remove the need for Ge integration. Split-diode design enables half-rate receivers, mitigating transistor speed limitations. An on-chip feedback loop locks the resonant defect detector to the laser wavelength, combating thermal upset. The 5 m optical link achieves 5 Gb/s at 3 pJ/b electrical and 13 pJ/b optical energy, in 0.18 μm (100 ps FO4) bulk CMOS memory periphery process.

Keywords

CMOS memory circuits; DRAM chips; circuit feedback; elemental semiconductors; integrated optics; optical links; optical resonators; optical storage; optical waveguides; silicon; DRAM; Si; bit rate 5 Gbit/s; bulk CMOS memory periphery process; deep-trench isolation; half-rate receivers; laser wavelength; monolithically-integrated chip-to-chip optical link; on-chip feedback loop; polysilicon resonant detectors; polysilicon waveguide integration; resonant defect detector; silicon-photonic link; size 0.18 mum; split-diode design; thermal upset; time 100 ps; transistor speed limitation mitigation; Optical fiber communication; Optical fibers; Optical receivers; Photonics; DRAM; Monolithic; bulk; optical; transceiver;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858377

Filename

6858377