Title :
A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS
Author :
Chang-Hyeon Lee ; Kabalican, Lindel ; Yan Ge ; Kwantono, Hendra ; Unruh, Greg ; Chambers, Mark ; Fujimori, Ichiro
Author_Institution :
Broadcom, Irvine, CA, USA
Abstract :
A fractional-N LCPLL in 28nm CMOS that uses vertical layout integration techniques to achieve area reduction is proposed. The design utilizes a multimetal layer interposed inductor pair that is stacked on top of the active PLL circuit elements, resulting in an area of 0.07mm2. The PLL covers a wide-frequency range from 2.7GHz to 7GHz, consuming a total power of 14mW. At 7GHz, the RMS jitter is 0.56ps at integer mode and 1.1ps at fractional mode.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; active networks; integrated circuit layout; microwave integrated circuits; phase locked loops; system-on-chip; CMOS; RMS jitter; active circuit elements; area reduction; fractional-N LCPLL; frequency 2.7 GHz to 7 GHz; integer mode; multimetal layer SoC technology; power 14 mW; size 28 nm; time 0.56 ps; time 1.1 ps; vertical layout integration techniques; Inductors; Jitter; Metals; Noise; Phase locked loops; Switches; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858390
