A 4.4–5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter

Author

Talegaonkar, Mrunmay ; Anand, Tejasvi ; Elkholy, Ahmed ; Elshazly, Amr ; Nandwana, Romesh Kumar ; Saxena, Shanky ; Young, B. ; Choi, Wan ; Hanumolu, Pavan Kumar

Author_Institution

Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A phase interpolator (PI) based fractional divider is used to improve the quantization noise shaping properties of a 1-bit ΔΣ frequency-to-digital converter (FDC). Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed FDC in place of a high resolution TDC and achieves -102dBc/Hz in-band phase noise and 852fs_rms integrated jitter (1k-40M) while generating 5.054GHz output from 31.25MHz input.

Keywords

CMOS digital integrated circuits; MMIC frequency convertors; delta-sigma modulation; digital phase locked loops; field effect MMIC; frequency dividers; ΔΣ frequency-to-digital converter; CMOS process; FDC; PI based fractional divider; digital fractional-N PLL; frequency 31.25 MHz; frequency 4.4 GHz to 5.4 GHz; frequency-to-digital converter; high resolution TDC; phase interpolator; prototype calibration-free fractional-N type-II PLL; quantization noise shaping properties; size 65 nm; time 852 fs; word length 1 bit; Bandwidth; Floors; Modulation; Phase locked loops; Phase noise; Quantization (signal);

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858392

Filename

6858392