Title :
A 65nm 10GHz pipelined MAC structure
Author :
Kashfi, Fatemeh ; Fakhraie, S. Mehdi ; Safari, Saeed
Author_Institution :
Sch. of ECE, Univ. of Tehran, Tehran
Abstract :
In this paper a pipelined 16times16+32 MAC structure is explained. This is a fused MAC which is using modified Booth encoding technique and a new low-voltage-swing 4:2 compressor. For the final adder, it is using low-voltage-swing carry-select structure. With this topology, we achieved a 5-stage pipelined MAC with 10 GHz clock frequency and 15 mW/GHz average power dissipation in 65 nm CMOS technology with 1.2 V power supply.
Keywords :
CMOS integrated circuits; digital signal processing chips; encoding; network topology; pipeline processing; power supply circuits; Booth encoding technique; CMOS technology; digital signal processors; frequency 10 GHz; low-voltage-swing carry-select structure; low-voltage-swing compressor; multiply-accumulate unit; pipelined MAC structure; power dissipation; power supply; size 65 nm; topology; voltage 1.2 V; Adders; CMOS technology; Clocks; Counting circuits; Encoding; Frequency; Logic; Power dissipation; Power supplies; Topology;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541454
