Title :
A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC
Author :
Bandyopadhyay, Abhishek ; Adams, Rene ; Khiem Nguyen ; Baginski, Paul ; Lamb, D. ; Tansley, Thomas
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
Abstract :
A continuous time 5-bit feed forward ΔΣ ADC architecture is presented, which measures 97.3 dB SNR, over 600 kHz bandwidth while consuming 31 mW/channel. This performance is achieved by using an ISI mitigation scheme and a 2nd-order DEM for 3-level DACs along with analog low power techniques. The 0.99mm2/channel chip was fabricated in 0.18um CMOS process, and achieves a FOM of 171.8 dB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; interference suppression; intersymbol interference; low-power electronics; 2nd-order DEM; 3-level DAC; CMOS process; ISI mitigation scheme; analog low power techniques; bandwidth 600 kHz; feedforward ADC architecture; intersymbol interference mitigation; multibit continuous time ΔΣ ADC; power 31 mW; second order dynamic element matching scheme; size 0.18 mum; word length 5 bit; Bandwidth; Clocks; Signal to noise ratio; Split gate flash memory cells; Switches; Topology;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858397
