Title :
An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS
Author :
Chan-Hsiang Weng ; Tzu-An Wei ; Alpman, Erkan ; Chang-Tsung Fu ; Yi-Ting Tseng ; Tsung-Hsien Lin
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A power-efficient continuous-time delta-sigma modulator (CTDSM) employing a single-amplifier biquad (SAB) based topology is proposed. The modulator incorporates a proposed twin-T SAB topology where the excess loop delay (ELD) is compensated by injecting a feedback signal into an internal node of the SAB while cooperating with an additional phase-compensation resistor. A low-power time-to-digital converter (TDC) with an embedded data weighted averaging (DWA) function is proposed as the quantizer, which mitigates the mismatch issue in the feedback DACs. Fabricated in 90nm CMOS, the proposed CTDSM achieves peak SNDR of 67.2dB over an 8.5MHz signal bandwidth, while consuming 4.3mW at 300MHz sampling frequency, and scores a FoM of 135fJ/conv.-step.
Keywords :
CMOS digital integrated circuits; amplifiers; biquadratic filters; circuit feedback; continuous time filters; delta-sigma modulation; error compensation; low-power electronics; time-digital conversion; CMOS process; DWA function; ELD compensation embedded twin-T SAB topology; SNDR CTDSM; TDC; circular TDC-based quantizer; embedded data weighted averaging function; excess loop delay; feedback DACs; feedback signal; frequency 300 MHz; low-power time-to-digital converter; phase-compensation resistor; power 4.3 mW; power-efficient continuous-time delta-sigma modulator; single-amplifier biquad based topology; size 90 nm; Bandwidth; CMOS integrated circuits; Clocks; Delays; Modulation; Power harmonic filters; Topology;
Conference_Titel :
VLSI Circuits Digest of Technical Papers, 2014 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4799-3327-3
DOI :
10.1109/VLSIC.2014.6858398
