A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS

Author

Shibasaki, T. ; Chaivipas, W. ; Yanfei Chen ; Doi, Yoshihito ; Hamada, Takahiro ; Takauchi, Hideki ; Mori, Takayoshi ; Koyanagi, Yoshio ; Tamura, H.

Author_Institution

Fujitsu Labs. Ltd., Kawasaki, Japan

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 56-Gb/s receiver front-end suited for baud-rate clock recovery is demonstrated in 20-nm CMOS. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with a bit error rate of less than 10^-12 with a 0.4UI margin in the bathtub curve. It occupies 0.27mm² and consumes 177mW of power from a 0.9-V supply.

Keywords

CMOS analogue integrated circuits; comparators (circuits); decision feedback equalisers; receivers; synchronisation; 1-tap speculative decision-feedback equalizer; CMOS process; CTLE; bathtub curve; baud-rate clock recovery; bit error rate; bit rate 56 Gbit/s; comparators; continuous-time linear equalizer; data decision; phase detection; power 177 mW; power consumption reduction; receiver front-end; size 20 nm; voltage 0.9 V; CMOS integrated circuits; Clocks; DH-HEMTs; Decision feedback equalizers; Phase detection; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858400

Filename

6858400