The effects of thread placement on the KSR1

Author

Wagner, T.D. ; Smirni, E. ; Apon, A.W. ; Madhukar, M. ; Dowdy, L.W.

Author_Institution

Dept. of Comput. Sci., Vanderbilt Univ., Nashville, TN, USA

fYear

1994

fDate

26-29 Apr 1994

Firstpage

618

Lastpage

624

Abstract

This paper describes a effects of thread placement on memory access times measurement study on the Kendall Square KSR1 multiprocessor. The KSR1 uses a conventional shared memory programming model in a distributed memory architecture based on a ring of rings of 64-bit superscalar microprocessors. Memory consists of local cache memories attached to each processor and is managed in a cache-only memory architecture (COMA) fashion. Experiments run on the KSR1 across a variety of thread configurations show that shared memory access is accelerated through strategic placement of threads which share data. The experiments “stress test” the automatic prefetching feature of the hardware. Strategies to keep the KSR1 memory access times nearly constant even when the number of participating threads increases are proposed

Keywords

buffer storage; concurrency control; distributed memory systems; parallel programming; shared memory systems; KSR1; Kendall Square KSR1 multiprocessor; automatic prefetching feature; cache-only memory architecture; distributed memory architecture; local cache memories; memory access times; shared memory access; shared memory programming model; thread configurations; thread placement; Acceleration; Automatic testing; Cache memory; Hardware; Memory architecture; Memory management; Microprocessors; Prefetching; Time measurement; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing Symposium, 1994. Proceedings., Eighth International

Conference_Location

Cancun

Print_ISBN

0-8186-5602-6

Type

conf

DOI

10.1109/IPPS.1994.288240

Filename

288240