A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer

Author

Quan Pan ; Zhengxiong Hou ; Yipeng Wang ; Yan Lu ; Wing-Hung Ki ; Keh Chung Wang ; Yue, C. Patrick

Author_Institution

Hong Kong Univ. of Sci. & Technol., Hong Kong, China

fYear

2014

fDate

10-13 June 2014

Firstpage

1

Lastpage

2

Abstract

A 65-nm CMOS monolithic optical receiver IC with on-chip photodetector (PD) using the p-well/deep-n-well (PW/DNW) junction is presented for short-range optical communication using 850-nm wavelength. An adaptive continuous-time linear equalizer (CTLE) with 33-dB tunable gain is employed to compensate for the limited PD responsivity and bandwidth. For 850-nm optical PRBS-15 inputs, the receiver achieves record data rates and efficiencies of 9 Gb/s at 5.35 pJ/bit and 18 Gb/s at 2.7 pJ/bit with the PD biased in 0.5-V standard mode and 12.3-V avalanche mode, respectively. The core chip occupies 0.23 mm² and consumes 48 mW.

Keywords

CMOS integrated circuits; adaptive equalisers; integrated optoelectronics; optical receivers; photodetectors; semiconductor junctions; CTLE; adaptive continuous-time linear equalizer; avalanche mode; bit rate 18 Gbit/s; bit rate 9 Gbit/s; data rates; fully integrated CMOS monolithic optical receiver IC; gain 33 dB; limited PD responsivity; on-chip photodetector; optical PRBS-15 inputs; p-well-deep-n-well junction; power 48 mW; short-range optical communication; size 65 nm; voltage 0.5 V; voltage 12.3 V; wavelength 850 nm; CMOS integrated circuits; CMOS technology; Frequency measurement; Optical fibers; Optical recording; Optical variables measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits Digest of Technical Papers, 2014 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4799-3327-3

Type

conf

DOI

10.1109/VLSIC.2014.6858402

Filename

6858402