Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing

Digital RF Processor (DRP^TM)-based GSM/EDGE transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. Using the concept of digital at the service of analog, DRP transmitters employ a number of estimation and compensation algorithms to provide robust performance in the presence of CMOS device variability. This paper describes digital techniques to counter the random and systematic mismatches in the amplitude path of the small-signal DRP transmitter. Furthermore, the DRP-based small signal polar EDGE transmitter utilizes a nonlinear digitally-controlled pre-power amplifier (DPA) with optimized power-added efficiency (PAE). The DPA is used for on-chip combination of the amplitude and phase modulation paths, which exhibit variable transfer characteristics due to process, voltage, temperature and aging. For stringent transmitter (TX) performance requirements, the DPA needs to be linearized in the dynamic TX operational environment. The techniques presented are employed in a commercial Texas Instruments single-chip GSM/EDGE radio realized in nanoscale CMOS.