Title :
Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement
Author :
Sun, Yi-Fa ; Liu, Chun-Nan ; Chen, Tse-Min ; Hsieh, Hsien-Ching ; Yeh, Jen-Chieh ; Chang, Yung-Chang
Author_Institution :
Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
The three-dimensional (3-D) stacking memory is good way to extend the local memory of embedded CPU and/or DSP by the through-silicon-vias (TSVs) technology. In this work, we show a multi-core system with 3-D stacking memory, and the stacking memory can be configured as instruction cache or local data memory for each DSP core. Due to the non-cacheable property of local memory, the programmers have to rethink the software algorithm and the data structure to efficiently use the extended memory space. To demonstrate the performance enhancement of 3-D system, this paper presents three enhanced multimedia applications for HW/SW co-simulation by the electronic system-level (ESL) virtual platform. According to the experimental results, the 3-D system performance can be improved by 30%~50% for assembly coded single-channel H.264 decoder and multi-channel H.264 decoder respectively, compared with traditional 2-D system. In addition, for a JPEG decoder compiled with C compiler, more than 6 times system performance can be improved by placing the data section, heap and stack structure from external DDR2 memory to the 3-D stacking memory.
Keywords :
cache storage; data structures; decoding; digital signal processing chips; memory architecture; multimedia computing; multiprocessing systems; software engineering; three-dimensional integrated circuits; 3D stacking memory architecture; 3D system performance enhancement; C compiler; DDR2 memory; ESL virtual platform; HW-SW cosimulation; JPEG decoder; TSV technology; assembly coded single-channel H.264 decoder; data structure; electronic system-level virtual platform; embedded CPU memory; extended memory space; instruction cache; local memory noncacheable property; multichannel H.264 decoder; multicore system; multimedia applications; multimedia performance; software algorithm; software refinement; stack structure; three-dimensional stacking memory; through-silicon-vias technology; Decoding; Digital signal processing; Memory management; Random access memory; Stacking; Through-silicon vias; 3-D IC; DSP; H.264; TSV; multimedia;
Conference_Titel :
High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems (HPCC-ICESS), 2012 IEEE 14th International Conference on
Conference_Location :
Liverpool
Print_ISBN :
978-1-4673-2164-8
DOI :
10.1109/HPCC.2012.236