Implications of technology scaling on leakage reduction techniques

Author

Tsai, Y.-F. ; Duarte, Duarte ; Vijaykrishnan, N. ; Irwin, M.J.

Author_Institution

Dept. of Comput. Sci. & Eng., Penn State Univ., USA

fYear

2003

fDate

2-6 June 2003

Firstpage

187

Lastpage

190

Abstract

The impact of technology scaling on three run-time leakage reduction techniques (input vector control, body bias control and power supply gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 0.25 um, 0.18 um, and 0.07 um technologies. HSPICE simulation results are estimations with various functional units and memory structures are presented to support a comprehensive analysis.

Keywords

SPICE; circuit optimisation; digital integrated circuits; integrated circuit layout; integrated circuit modelling; leakage currents; low-power electronics; memory architecture; power electronics; wafer-scale integration; 0.07 mm; 0.18 mum; 0.25 mum; HSPICE simulation; body bias control; comprehensive analysis; input vector control; leakage reduction techniques; power supply gating; technology scaling implications; Analytical models; CMOS technology; Circuits; Dynamic voltage scaling; Permission; Power supplies; Runtime; Semiconductor device measurement; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2003. Proceedings

Print_ISBN

1-58113-688-9

Type

conf

DOI

10.1109/DAC.2003.1218939

Filename

1218939