Presetting pulse-based flip-flop

In this paper, presetting pulse-based flip-flop (PSPFF) is proposed. The flip-flop briefly presets its storage nodes to a medium voltage level between VDD and VSS just before input capturing. This presetting operation allows the proposed flip- flop to be faster and more clock-skew tolerant than conventional pulse-based flip-flops. Comparison results using a 80-nm CMOS process technology indicate that PSPFF has 22% improvement on clock-skew tolerance, 20% decrease of data-to-output delay, 22% reduction of power-delay product, and 21% reduction of layout area, as compared to PCSPFF.